The present invention relates to a plasma display apparatus. More particularly, the present invention relates to an improvement of a drive circuit that applies a voltage pulse to an electrode at which a sustain discharge is caused to occur.
The plasma display apparatus has been put to practical use as a flat display and is a thin display apparatus of a high intensity. FIG. 1 is a diagram that shows the general structure of a conventional three-electrode AC-driven plasma display apparatus. As shown schematically, the plasma display apparatus comprises a plasma display panel (PDP) 1 composed of two substrates, between which a discharge gas is sealed, each substrate having plural X electrodes (X1, X2, X3, . . . , Xn) and Y electrodes (Y1, Y2, Y3, . . . , Yn) arranged adjacently, plural address electrodes (A1, A2, A3, . . . , Am) arranged in the intersecting direction thereto, and fluorescent materials arranged at intersecting parts, an address driver 2 that applies pulses such as an address pulse to the address electrode, an X common driver 3 that applies pulses such as a sustain discharge pulse to the X electrode, a scan driver 4 that applies pulses such as a scan pulse sequentially to the Y electrode, a Y common driver 5 that applies pulses such as a sustain discharge pulse to be applied to the Y electrode to the scan driver 4, and a control circuit 6 that controls each section, and the control circuit 6 further comprises a display data control section 7 that includes a frame memory and a drive control circuit 8 composed of a scan driver control section 9 and a common driver control section 10. As the plasma display apparatus is widely known, a more detailed description of the entire apparatus is omitted here and only the X common driver 3 and the Y common driver 5 that relate to the present invention are further described. The X common driver, the scan driver, and the Y common driver of the plasma display apparatus have been disclosed, for example, in Japanese Unexamined Patent Publication (Kokai) No. 9-68946 and Japanese Unexamined Patent Publication (Kokai) No. 2000-194316.
FIG. 2 is a diagram that shows an example of the structure of the X common driver, the scan driver, and the Y common driver, which have been disclosed as described above. Plural X electrodes are connected commonly and driven by the X common driver 3. The X common driver 3 comprises output devices (transistors) Q8, Q9, Q10, and Q11, which are provided between the common X electrode terminal and a voltage source +Vs1, between that and −Vs2, between that and +Vx, and between that and −Vwx, respectively. By turning on any one of the transistors, the corresponding voltage is supplied to the common X electrode terminal. The scan driver 4 is composed of individual driver provided for each Y electrode and each individual driver comprises transistors Q1 and Q2, and diodes D1 and D2 provided in parallel thereto. Each of one end of transistors Q1 and Q2, and diodes D1 and D2 of each individual driver is connected to each Y electrode and each of the other end is connected commonly to the Y common driver 5. The Y common driver 5 comprises transistors Q3, Q4, Q5, Q6, and Q7, which are provided between the line from the scan driver 4 and the voltage source +Vs1, between that and −Vs2, between that and +Vwy, between that and +Vy, and between that and a ground (GND), respectively, and the transistors Q3, Q5, and Q7 are connected to the transistor Q1 and the diode D1, and the transistors Q4 35 and Q6, to the transistor Q2 and the diode D2.
In the reset period, Q5 and Q11 are turned on while the other transistors are turned off, and +Vwy is applied to the Y electrode and −Vwx is applied to the X electrode to generate an entire write and erase pulse that puts the display cells on the panel 1 into a uniform state. At this time, the voltage +Vwy is applied to the Y electrode via Q5 and D1. In the address period, Q6, Q7, and Q10 are turned on while the other transistors are turned off, and +Vx is applied to the X electrode, the voltage +Vy, to the terminal of Q2, and GND is applied to the terminal of Q1. With this state, an scan pulse that turns Q1 on and Q2 off is applied sequentially to individual drivers. At this time, in individual drives to which a scan pulse is not applied, Q1 is turned off and Q2 is turned on, therefore, GND is applied to the Y electrode, to which the scan pulse has been applied, via Q1, +Vy is applied to the other Y electrodes via Q2, and an address discharge is caused to occur between the address electrode to which a positive data voltage is applied and the Y electrode to which the scan pulse has been applied. In this way, each cell in the panel is put into a state according to the display data.
In the sustain discharge period, while Q1, Q2, Q5–Q7, Q10, and Q11 are being kept off, Q3 and Q9, and Q4 and Q8 are alternately turned on. These transistors are called the sustain transistors here. In this way, +Vs1 and −Vs2 are alternately applied to the Y electrode and the X electrode and a sustain discharge is caused to occur for display in the cell in which an address discharge has been caused to occur in the address period. At this time, if Q3 is turned on, +Vs1 is applied to the Y electrode via D1, and if Q4 is turned on, −Vs2 is applied to the Y electrode via D2. In other words, the voltage Vs1+Vs2 is alternately applied to the X electrode and the Y electrode with a reversed polarity in the sustain discharge period. This voltage is called the sustain voltage here.
The example described above is only one of various examples, and there are various modifications as to which kind of voltage is applied in the reset period, the address period, and the sustain discharge period, and there are also various modifications of the scan driver 4, the Y common driver 5, and the X common driver 6.
The scan pulse needs to be applied sequentially to each Y electrode, therefore, Q1 and Q2 that relate to the application of the scan pulse are required to be capable of high-speed operations. Moreover, since the number of times a sustain discharge is caused to occur affects the display intensity and as many sustain discharges as possible need to be caused to occur in a fixed period, the sustain transistors Q3, Q4, Q8, and Q9, which relate to the application of the sustain discharge pulse, are also required to be capable of high-speed operations. On the other hand, in the plasma display apparatus, it is necessary to apply a high voltage to each electrode in order to cause a discharge to occur, therefore, the transistors are required to have a high withstand voltage to resist a great voltage. A transistor, which has a high withstand voltage but has a relatively low operating speed, or a transistor, which has a high operating speed but has a relatively low withstand voltage, can be manufactured at a low cost, but that which has not only a high withstand voltage but also a high operating speed is costly.
Among the transistors in FIG. 2, the operating speed of Q6, Q7, Q10, and Q11 can be relatively low because they do not directly relate to the application of the scan pulse and the sustain discharge pulse, which requires a high-speed operation. Although a high-speed operation is required for Q1 and Q2, the withstand voltage thereof can be relatively small, because D1 and D2 are provided in parallel thereto, the voltages to be applied are +Vy and GND, and the difference in voltage therebetween is relatively small.
Contrary to this, the sustain transistors Q3, Q4, Q8, and Q9 need to be capable of high-speed operations and a high voltage is applied thereto as well. As shown in FIG. 2, in the X common driver 3, the X electrode connected commonly is connected to +Vs1, −Vs2, +Vx, and −Vwx via Q8, Q9, Q10, and Q11, respectively, and when Q8 is on, +Vs1 is applied to the common X electrode therefore the voltage Vs1+Vs2 (sustain voltage) is applied across Q9, and when Q10 is on, +Vx is applied to the common X electrode therefore the voltage Vx+Vs2 is applied across Q9. Similarly, Vs1+Vs2 or Vs1+Vwx is applied across Q8. Therefore, if Vs1>Vx and Vs2>Vwx, the transistors Q8 and Q9 are required only to have a withstand voltage of Vs1+Vs2 or greater, that is, the sustain voltage. If Vx>Vs1, Q9 needs to have a withstand voltage of Vx+Vs2 or greater, and if Vwx>Vs2, Q8 needs to have a withstand voltage of Vs1+Vwx or greater. As described above, the transistors Q8 and Q9 need to have a withstand voltage of the sustain voltage or greater because a sustain discharge is applied thereto, and if Vx>Vs1 or Vwx>Vs2, a greater withstand voltage is required.
In the Y common driver 5, the anode of the diode D1 is connected to +Vs1, +vwy, and GND via Q3, Q5, and Q7, respectively, and the cathode of the diode D2 is connected to −Vs2 and +Vy via Q4 and Q6, respectively. When Q3 is on, +Vs1 is applied to each Y electrode, and the voltage is further applied to the terminal of Q4 via D2, therefore, the voltage Vs1+Vs2 (sustain voltage) is applied across Q4 as a result. Similarly, when Q5 is on, the voltage Vwy+Vs2 is applied across Q4, and when Q4 is on, Vs1+Vs2 is applied across Q3. When Q6 is on, the voltage Vy+Vs2 is applied across Q4. Therefore, the transistors Q3 and Q4 are required to have a withstand voltage equal to or greater than the sustain voltage because the sustain discharge pulse is applied thereto, and Q3 is required to have a greater withstand voltage if Vwy>Vs1 or Vy>Vs1.
Generally, when the voltage rating of the sustain output device (transistor) is high, the saturation voltage of the device is also high and, in order to lower the saturation voltage, measures such as to drive plural devices in parallel and to use a device the chip size and the size of which are large will be required, resulting in a problem that the cost is raised accordingly.